The present invention relates to Complementary Metal Oxide Semiconductor (CMOS) devices, and more specifically, spacer formation in dual epitaxial (epi) growth CMOS applications.
CMOS is heavily used in the manufacture of integrated circuits. A typical CMOS device includes two types of transistors, a P-type metal-oxide-semiconductor field effect transistor (MOSFET) (PFET) and an N-type MOSFET (NFET).
Three-dimensional semiconductor devices, such as fin-type semiconductor devices (referred to as finFETs), typically include dielectric gate spacers formed on sidewalls of the gate stack to isolate the gate stack from the adjacent source/drain (S/D) regions.
In the fabrication of semiconductor devices on semiconductor wafers, the designed specifications of the devices may not always be achieved when the final devices are formed. As CMOS devices are scaled down, dual source-drain epitaxial (epi) deposition process can be implemented to enhance carrier mobility and improve device performance. However, the scaling of next generation technology has resulted in problems. For example, the conventional process scheme requires overlap of the N-FET transistor and P-FET transistor to avoid dual spacer etch and resulting epitaxial nodule defects. Moreover, there is no reliable overlap for mid-ultraviolet (MUV) lithography. In addition, conventional dual epi processes can lead to differing spacer thicknesses on the PFET and NFET. Such uneven spacing, for example a thicker NFET spacer, can degrade device performance. Moreover, differing middle of the line (MOL) spacer gaps that can result in conventional dual epi processes are not compatible with 7 nanometer (7 NM) technology nodes currently in demand.